The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. It has been observed that such scaling down introduces challenges in maintaining process variations at acceptable levels. For example, as process geometries continue to decrease from 65 to 45 nanometer and beyond, a profile of a gate stack becomes critical to IC device performance. Process variations fabricate IC devices having varying gate profiles, which may stray from a target gate profile. Conventional IC device manufacturing lacks a way to manage and/or control the formation of gate stacks, wherein completed gate stacks exhibit the desired target gate profile.
Accordingly, what is needed is a method for fabricating an IC device that addresses the above stated issues.